This application claims the benefit of a Japanese Patent Application No.2001-323281 filed Oct. 22, 2001, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to rush current suppression circuits, and more particularly to a rush current suppression circuit for a power supply.
In electronic equipments which handle electronic information, there are demands to reduce voltages and to increase currents, in large scale integrated circuits (LSIs). In addition, there are demands to reduce the size and to improve the efficiency of power supply units which supply power to such LSIs.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing an example of a conceivable rush current suppression circuit. In FIG. 1, Ei denotes an input power supply or input power supply voltage, Ec denotes an output voltage, and a reference numeral 1 denotes a load with respect to a power supply circuit. In the power supply circuit, a field effect transistor FET1 is inserted in series to a loop of the circuit, a resistor R1 has one end thereof connected to an output line, and a Zenner diode ZD1 is connected in series to the resistor R1. An anode of the Zenner diode ZD1 is connected to a gate G of the transistor FET1.
A smoothing capacitor C1 is connected to an output end of the power supply Ei. A rapid discharge and delay circuit 2 has one end thereof connected to the anode of the Zenner diode ZD1, and the other end thereof connected to a common line of the power supply Ei.
The rapid discharge and delay circuit 2 includes a diode D1, a transistor TR1 having an emitter thereof connected to a cathode of the diode D1, a resistor R3 connected between a collector of the transistor TR1 and the common line, and a resistor R2 having one end thereof connected to a base of the transistor TR1 and the other end thereof connected to the common line. The base of the transistor TR1 and an anode of the diode D1 are connected by a node which connects to the anode of the Zenner diode ZD1.
A description will now be given of the operation of the power supply circuit shown in FIG. 1, by referring to FIG. 2. FIG. 2 is a timing chart for explaining signal waveforms at various parts of the circuit shown in FIG. 1. In FIGS. 2, (a) shows the input power supply voltage Ei, (b) shows the output voltage Ec, (c) shows a voltage VC2 applied to the capacitor C2 (or a gate voltage VGS of the transistor FET1), and (d) shows a load current Ii.
(1) When Input Power Supply Voltage Ei Is Applied:
When the input power supply voltage Ei is applied to the circuit at a time t1 as shown in FIG. 2(a), the input power supply voltage Ei is applied to the gate G of the transistor FET1 via the resistor R1 and the Zenner diode ZD1. At the same time, the voltage VC2 applied on the capacitor C2 of the rapid discharge and delay circuit 2 gradually increases as shown in FIG. 2(c) because charges are gradually supplied to the capacitor C2. The voltage VC2 of the capacitor C2 is applied to the transistor FET1 as the gate voltage VGS.
When the gate voltage VGS exceeds a level which turns the transistor FET1 ON at a time t2, the transistor FET1 turns ON as shown in FIG. 2(b). Hence, a rush current is suppressed by turning ON the transistor FET1 after a delay time from the time t1 when the input power supply voltage Ei is applied. As a result, a charging current starts to flow to the smoothing capacitor C1, and the output voltage Ec increases as shown in FIG. 2(b). Consequently, an excessively large rush current flows as the load current Ii, as shown in FIG. 2(d).
(2) When Instantaneous Cutoff of Input Power Supply (Instantaneous Short-Circuit Failure of Input Power Supply Ei) Occurs:
At a time t3 shown in FIG. 2(a), both ends of the input power supply Ei are short-circuited and the input power supply voltage Ei becomes zero. In this state, the charge accumulated in the smoothing capacitor C1 is discharged. A discharge loop of this discharge includes the input power supply Ei and an internal diode of the transistor FET1, that is, a body diode of the transistor FET1 indicated by a dotted line in FIG. 1. When the charge of the smoothing capacitor C1 is discharged, a peak current flows in a reverse direction as shown in FIG. 2(d) in the load current Ii at the time of the instantaneous cutoff of the input power supply Ei.
At the same time, when the charged voltage of the smoothing capacitor C1 becomes less than or equal to a Zenner voltage of the Zenner diode ZD1, the transistor TR1 of the rapid discharge and delay circuit 2 turns ON. Hence, the rapid discharge and delay circuit 2 operates as a rapid discharge circuit, and rapidly discharges the charge accumulated in the capacitor C2. As a result, the gate voltage VGS is rapidly discharged to zero as shown in FIG. 2(c), to thereby turn OFF the transistor FET1.
(3) When Input Power Supply Resumes Power:
It is assumed that the power of the input power supply Ei resumes power from a time t4. Since the voltage applied across both ends of the smoothing capacitor C1 is approximately zero in this state, the operation from the time t4 when the input power supply Ei resumes power becomes the same as the operation when the input power supply voltage Ei is newly applied. Accordingly, a voltage having the same voltage as the input power supply Ei is applied to the smoothing capacitor C1, and the rush current having the same value as the case (1) described above flows.
At the time of the instantaneous cutoff of the input power supply Ei, the charge accumulated in the smoothing capacitor C1 is discharged via the discharge loop via the body diode of the transistor FET1, to thereby rapidly reduce the charge of the capacitor C1. For this reason, when the input power supply Ei resumes power, the input power supply voltage Ei is directly applied to the smoothing capacitor C1 when the input power supply Ei resumes power, and the excessively large rush current flows. The flow of such an excessively large rush current is undesirable for the input power supply Ei and for the electronic equipments which uses the input power supply Ei. There is also a possibility that the rush current will affect other apparatuses undesirably.
Accordingly, it is a general object of the present invention to provide a novel and useful rush current suppression circuit in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a rush current suppression circuit which prevents an excessive decrease in a voltage of a smoothing capacitor, and prevent flow of an excessively large current.
Still another object of the present invention is to provide a rush current suppression circuit adapted to a power supply circuit which includes a common line and an input voltage detection circuit and supplies power from an input power supply via a switching circuit, comprising a smoothing capacitor coupled to an output end of the power supply circuit; and a rapid discharge and delay circuit, coupled to the input voltage detection circuit, carrying out a rapid discharge and a time delay and controlling the switching circuit, where the switching circuit includes first and second field effect transistors which are coupled in series to the common line of the power supply circuit, and the first and second field effect transistors have sources which are coupled to each other and gates which are coupled to each other and driven by the rapid discharge and delay circuit. According to the rush current suppression circuit of the present invention, it is possible to prevent an excessive decrease in a voltage of the smoothing capacitor, and prevent flow of an excessively large current.
A further object of the present invention is to provide a rush current suppression circuit connectable to a power supply circuit which is provided with a common line and an input voltage detection circuit and supplies power from an input power supply, comprising a smoothing capacitor which is coupled to an output end of the power supply circuit; a rapid discharge and delay circuit which is coupled to the input voltage detection circuit and carries out a rapid discharge and a time delay; and a switching circuit through which the power from the input power supply is supplied under control of the rapid discharge and delay circuit, where the switching circuit includes first and second field effect transistors which are coupled in series to the common line of the power supply circuit, and the first and second field effect transistors have sources which are coupled to each other and gates which are coupled to each other and driven by the rapid discharge and delay circuit. According to the rush current suppression circuit of the present invention, it is possible to prevent an excessive decrease in a voltage of the smoothing capacitor, and prevent flow of an excessively large current.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.